Program


Day 1: 13-12-2019
08:00 09:00 Registration
15:00 15:15 Opening remarks
15:15 16:15 Keynote – Subhasish Mitra
16:15 16:30 Break
16:30 17:20 Session: Test Generation I
17:20 17:30 Short Break
17:30 18:20 Session: Verification and Error Tolerant Computing
19:00 20:30 Dinner
Day 2: 14-12-2019
08:00 09:00 Registration
09:00 10:00 Keynote – Ramesh Karri
10:00 10:20 Break
10:20 11:35 Session: Low Power test
11:35 13:30 Lunch
13:30 14:30 Keynote – Nilanjan Mukherjee
14:30 14:50 Short Break
14:50 16:05 Session: Test Generation II
16:05 16:25 Break
16:25 18:00 Session: Security on Test

 

Session: Test Generation I
ID: 10 STIL Test Pattern Generation Enhancement in Mixed-Signal Design
ID: 13 PI Oriented Heuristic for Dynamic Test Compaction
Session: Verification and Error Tolerant Computing
ID: 5 Aquila: A Methodology for Achieving Fine-grained Bug Localization during Design Verification
ID: 11 Extension of an Approximate Voting Scheme IDMR for Fail-Operational Systems
Session: Low Power Test
ID: 6 LPSCADER : A Pre-DFT Tool to Determine Scan Order for Low Power Scan Testing
ID: 12 An approach of bin packing technique for test cost optimization of core based non stacked integrated circuits
ID: 2 A Don’t Care Identification-Filling Co-Optimization Method for Low Capture Power Testing Using Partial MaxSAT
Session: Test Generation II
ID: 1 A Compaction Method of Test Sensitization States on Controller Augmentation
ID: 7 Compacted Seed Generation for Built-in Self-Diagnosis of Delay Faults
ID: 8 Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths
Session: Security for Test
ID: 4 Reconfigurable-LUT Based Attack on FPGA Implementations of AES
ID: 9 ANP: A Self-Reference-Based Random Variation Aware Hardware Trojan Detection Method