Day 1: 13-12-2019
08:00 09:00 Registration
14:30 14:45 Opening remarks
14:45 15:45 Keynote – Subhasish Mitra
15:45 16:00 Break
16:00 17:00 Session: Test Generation I
17:00 17:15 Short Break
17:15 18:30 Session: Verification and Error Tolerant Computing
19:00 20:30 Dinner
Day 2: 14-12-2019
08:00 09:00 Registration
09:00 10:00 Keynote – Ramesh Karri
10:00 10:15 Break
10:15 11:30 Session: Low Power test
11:30 13:00 Lunch
13:00 14:00 Keynote – Nilanjan Mukherjee
14:00 14:15 Break
14:15 16:00 Session: Test Generation II
16:00 16:15 Short Break
16:15 18:00 Session: Security on Test


Session: Test Generation I
ID: 10 STIL Test Pattern Generation Enhancement in Mixed Signal Design
ID: 13 PI Oriented Heuristic for Dynamic Test Compaction
Session: Verification and Error Tolerant Computing
ID: 5 Aquila: A Methodology for Achieving Fine-grained Bug Localization during Design Verification
ID: 11 Extension of an Approximate Voting Scheme IDMR for Fail-Operational Systems
Session: Low Power Test
ID: 6 LPSCADER : A Pre-DFT Tool to Determine Scan Order for Low Power Scan Testing
ID: 12 An approach of bin packing technique for test cost optimization of core based non stacked integrated circuits
ID: 2 A Don’t Care Identification-Filling Co-Optimization Method for Low Capture Power Testing Using Partial MaxSAT
Session: Test Generation II
ID: 1 A Compaction Method of Test Sensitization States on Controller Augmentation
ID: 7 Compacted Seed Generation for Built-in Self-Diagnosis of Delay Faults
ID: 8 Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths
Session: Security for Test
ID: 3 An Approach Towards Resisting Side-Channel Attacks for Secured Testing of Advanced Encryption Algorithm (AES) Cryptochip
ID: 4 Reconfigurable-LUT Based Attack on FPGA Implementations of AES
ID: 9 ANP: A Self-Reference-Based Random Variation Aware Hardware Trojan Detection Method