Tutorial 1: High-Speed I/O DFT and Testing in High Volume Manufacturing- Salem Abdennadher, Intel Corporation

With advances in VLSI technology, packaging and architecture, Systems on Chip (SoC) continue to increase in complexity. Increasing complexity has resulted in an unprecedented increase in design errors, manufacturing flaws and customer returns related to High-Speed I/O (HSIO) circuits. This tutorial presents challenges and existing techniques to meet test complexity of HSIO and methodologies needed to achieve the high-quality usually mandated by the critical applications such as automotive and medical, etc. Both system and block level test techniques with particular emphasis on DFT/BIST based methods and their suitability to production level environment are presented in this tutorial. Additionally, this tutorial includes a section on Analog Defects and detection methods using DFT and BIST techniques.

Tutorial 2: Safety and Security in Automotive 2.0 Era, Srivaths Ravi (Texas Instruments), Prasanth Viswanathan Pillai (Texas Instruments)

The increasing semiconductor consumption has been spurred by a revolution witnessed in the automotive industry. The integration of electronics and networking into conventional automobile driven by infotainment and ADAS a few years back is accelerated by megatrends of EV/HEV, autonomous driving and shared mobility. These trends, termed sometimes as Automotive 2.0, drive various requirements into the semiconductors being sourced. Of these, safety and security requirements are becoming paramount due to their impact and liability. This tutorial leverages the authors’ experiences in driving safety and security as a part of semiconductor development cycles. By breaking down complex system requirements into foundational ones at semiconductor level, the tutorial is intended to provide an accessible treatment of the subject for any semiconductor developer.

Tutorial 3: Scan Test Escapes, New Fault Models, and the Growing Need for Functional System Level Tests: Prof. Adit D. Singh (Auburn University)

This tutorial aims at understanding the increasing use of functional system level tests (SLTs) as an additional final defect screen before processor SOCs are shipped for assembly. For this, we take an in-depth look at traditional scan based Stuck-at and TDF tests to understand potential sources of test escapes. We also extensively discuss the effectiveness of new test generation methodologies such as Cell Aware, Gate Exhaustive, Transistor Stuck-Open, and Timing Aware in plugging these structural test holes. Based on this, we identify failures that can still remain undetected by low cost scan structural tests, and require the use of expensive functional SLTs to achieve desired defect levels. In conclusion, we suggest strategies to minimize use SLTs without impacting defect levels.

Tutorial 4: DFT for Low Power Design: Jais Abraham (Qualcomm India), Arvind Jain(Qualcomm India), Nilanjan Mukherjee(Mentor USA), Shamitha Rao(Mentor India)