Program Technical


Program Schedule : Tutorials

Day 1 (10th December 2019, Tuesday)

09:00 – 09.30

Registration

09:30 – 11:00

Tutorial 1: High-Speed I/O DFT and Testing in High Volume Manufacturing

By Salem Abdennadher, Intel Corporation

Tutorial 2: Safety and Security in Automotive 2.0 Era

By Srivaths Ravi (Texas Instruments), Prasanth Viswanathan Pillai (Texas Instruments)

11:00 – 11:30

Tea Break

11:30 – 13:00

Tutorial 1: High-Speed I/O DFT and Testing in High Volume Manufacturing>

By Salem Abdennadher, Intel Corporation

Tutorial 2: Safety and Security in Automotive 2.0 Era

By Srivaths Ravi (Texas Instruments), Prasanth Viswanathan Pillai (Texas Instruments)

13:00 – 14:00

Lunch Break

14:00 – 15:30

Tutorial 3: Scan Test Escapes, New Fault Models, and the Growing Need for Functional System Level Tests

By Prof. Adit D. Singh (Auburn University)

Tutorial 4: DFT for Low Power Design

By Jais Abraham (Qualcomm India), Arvind Jain (Qualcomm India), Nilanjan Mukherjee (Mentor USA), Shamitha Rao (Mentor India)

15:30 – 16:00

Tea Break

16:00 – 17:30

Tutorial 3: Scan Test Escapes, New Fault Models, and the Growing Need for Functional System Level Tests

By Prof. Adit D. Singh (Auburn University)

Tutorial 4: DFT for Low Power Design

By Jais Abraham (Qualcomm India), Arvind Jain (Qualcomm India), Nilanjan Mukherjee (Mentor USA), Shamitha Rao (Mentor India)

18:00 – 20:00

Inauguration of ATS 2019

 

 

ATS 2019 Main Symposium

Day 1: 11-Dec-19

8:00 – 9:00 Registration
9:00 – 9:30 Opening remarks
9:30 – 10:30

Chair: Bhargab Bhattacharya, ISI Calcutta

10:30 – 11:00 Tea Break
11:00 – 12:00

Chair: Michiko Inuoe, Nara Institute of Science and Technology, Japan

12:00 – 13:15 A1 – AI Methods B1 –  ATS Steering Committee Meeting
C1 – PhD Contest
12:00 – 12:25 Deep Learning Based Test Compression Analyzer

Authors: Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar Reddy, Chun-Cheng Hu and Chong-Siao Ye

Resilient and Cost-effective Architectures and Design Methodologies for Stacked Three Dimensional Integrated Circuits
Raviteja P Reddy, Indian Institute of Technology, Hyderabad, India

 

Design, Analysis and Implementation of a Physically Unclonable Function based Authentication Framework for Internet-of-Things
Urbi Chatterjee, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur

 

ENHANCING SECURITY AND RELIABILITY OF HETEROGENEOUS IPS FOR SOC FPGAS
J. Kokila, Department of Computer Science and Engineering, National Institute of Technology, Tiruhirappalli, Tamil Nadu, INDIA

 

Enhanced Detection and Prevention Techniques to Ensure a Secured Hardware with Improved Performance Metrics
Sree Ranjani Rajendran, Department of Electronics Communication Engineering, Amrita School of Engineering, Coimbatore, India

 

FPGA INTERCONNECT RESOURCES TESTING
Shukla Banik, Department of Computer Science & Engineering National Institute of Technology, India
12:25 – 12:50 Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications

Authors: Elbruz Ozen and Alex Orailoglu

12:50 – 13:15 Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training

Authors: Spencer Millican, Yang Sun, Soham Roy and Vishwani Agrawal

13:15 – 14:15 Lunch Break
14:15 – 15:30 A2 – ATPG/BIST
B2 – Session Featuring Early-Career Women Researchers

Chair: Cecilia Metra, University of Bologna, Italy and Krishnendu Chakrabarty, Duke University, USA

C2 – PhD Contest (cont’d)
14:15 – 14:40 TEA: A Test Generation Algorithm for Designs with Timing Exceptions

Authors: Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab and Irith Pomeranz

Tanusree Kaibartta, IIT(ISM) Dhanbad

 

Urbi Chatterjee, Indian Institute of Technology Kharagpur

 

Ruchira Naskar, IIEST, Shibpur

 

Kasturi Ghosh, IIEST, Shibpur

 

Debasri Saha, University of Calcutta

 

Neha Gupta, Indian Institute of Technology Indore

 

Moumita Chakraborty, University of Calcutta

 

Sree Ranjani R CV, Indian Institute of Technology Madras
Application Aware Functional Safety Analysis Techniques
Prasanth V, Department of Electrical Communication, Indian Institute of Science, Bangalore.

 

FPGA IMPLEMENTATION OF HIGH PERFORMANCE TESTABLE LOGIC INSERTION IN BIT-SLICED ARCHITECTURE DESIGN
AYAN PALCHAUDHURI, DEPARTMENT OF ELECTRONICS Affiliation AND ELECTRICAL COMMUNICATION ENGINEERING, INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR

 

Self Aware Nature Inspired Approaches Ensuring Embedded Security
Krishnendu Guha, A. K. Choudhury School of Information Technology, University of Calcutta

 

HARDWARE IP PROTECTION USING LOGIC ENCRYPTION AND WATERMARKING
RAJIT KARMAKAR,INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR KHARAGPUR, INDIA
14:40 – 15:05 Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test

Authors: Manobendra Nath Mondal, Animesh Basak Chowdhury, Manjari Pradhan, Susmita Sur-Kolay and Bhargab B. Bhattacharya

15:05 – 15:30 A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures

Authors: Yushiro Hiramoto, Satoshi Ohtake and Hiroshi Takahashi

15:30 – 16:00 Tea Break
16:00 – 21:00 Social event – ‘An Evening on Kolkata Ganges’ and dinner

Day 2: 12-Dec-19

8:00 – 9:00 Registration
9:00 – 10:00

Chair: Debesh Das, Jadavpur University

10:00 – 11:00

Chair: Abhijit Chatterjee, Georgia Tech

11:00 – 11:30 Tea Break
11:30 – 12:45 A3 – Testing AI Chips B3 – Memory C3 – Industry 1
11:30 – 11:55 Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications

Authors: Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song and Xiaoqing Wen

11:55 – 12:20 Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection

Authors: Saranyu Chattopadhyay, Preeti Kumari, Biswajit Ray and Rajat Subhra Chakraborty

12:20 – 12:45 Self-Checking Residue Number System for Low-Power Reliable Neural Network

Author: Tsung-Chu Huang

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications

Authors: Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen and Xiaoqing Wen

12:45 – 13:45 Lunch Break
13:45 – 14:45

Chair: Dipanwita Roy Chowdhury, IIT KGP

14:45 – 16:10 A4 – SW Test & BIST
B4 – Test Education

Chair: Susmita Sur-Kolay, ISI, Kolkata and Rubin Parekhji, Texas Instruments, India

C4 – Security Special Session *High School Posters (Lobby)
14:45 – 15:10 Can Monitoring System State + Instruction Sequences aid Malware Detection?

Authors: Aditya Rohan, Kanad Basu and Ramesh Karri

Recruiting Fault Tolerance Techniques for Microprocessor Security

Authors:   Vinay B. Y. Kumar, Suman Deb, Rupesh Kumar, Mustafa Khairallah, Anupam Chattopadhyay and Avi Mendelson

15:10 – 15:35 Effective Fault Localization using Fisher’s Test

Authors: Arpita Dutta, Shubham Shankar, Krishna Kunal and Rajib Mall

Deep Learning based Diagnostics for Rowhammer Protection of DRAM Chips

Authors: Anirban Chakraborty, Manaar Alam and Debdeep Mukhopadhyay

15:35 – 16:00 Reinforcement-Learning Based Test Program Generation for Software-Based Self-Test

Authors: Ching-Yuan Chen and Jiun-Lang Huang

Towards Verifiably Secure Systems-on-Chip Platforms

Authors: Sujit Muduli and , Pramod Subramanyan

16:00 – 16:10 Dynamic Remapping Clusters for Low Latency Fault Tolerant Cache design in Chip Multiprocessor

Authors: Avishek Choudhury, Brototi Mondal and Biplab K Sikdar

Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level

Authors: Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok and Fawnizu Azmadi Hussin

16:10 – 16:40 Tea Break
16:40 – 18:10 Panel Discussion

Title: Bringing Intelligence (Artificial) to Test

Panelist: Srivaths Ravi (TI), Subhadip Kundu (QUALCOMM), Kanad Basu (UT Dallas), Thryambak Chandilya (Synopsys)

Moderator: Navin Bishnoi (Global Foundries, Bangalore)

18:10 – 18:30 Tea Break
18:30 – 19:30

Chair: Krishnendu Chakrabarty, Duke University, USA

19:30 – 20:30 A cultural program “A Tryst with Colors of India” followed by a Banquet dinner

Day 3: 13-Dec-19

8:00 – 9:00 Registration
9:00 – 10:00

Chair: James Chien-Mo Li, NTU Taipei, Taiwan

10:00 – 11:15 A5 – Validation and Diagnosis

Chair: Jais Abraham, Qualcomm India

B5 – Security C5 – Industry 2
10:00 – 10:25 Regular paper: Validating Multi-processor Cache Coherence Mechanisms Under Diminished Observability

Authors: Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita and Virendra Singh
Speaker: Binod Kumar, IIT Bombay, Mumbai

Net Classification Based on SCOAP and Net Structural Features for Hardware Trojan Detection

Authors: Chee Hoo Kok, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo and Fawnizu Azmadi Hussin

10:25 – 10:50 Embedded talk: Revisiting Scan Chain Diagnosis and its Efficiency in light of Machine Learning Algorithms

Author: Shubadip Kundu
Speaker: Shubadip Kundu, Qualcomm USA

GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network

Authors: Renjie Lu, Haihua Shen, Yu Su, Huawei Li and Xiaowei Li

10:50 – 11:15 Embedded talk: Towards Secure and Trustworthy Microfludic Biochips

Author: Sukanta Bhattacharjee
Speaker: Sukanta Bhattacharjee, IIT Guwahati

Efficient Testing of Physically Unclonable Functions for Uniqueness

Authors: Leandro Santiago de Araújo, Vinay C. Patil, Leandro Leandro Augusto Justen Marzulo, Felipe Maia Galvão França and Sandip Kundu

11:15 – 11:45 Tea Break
11:45 – 12:35 A6 – Verification B6 – Analog Test C6 – Emerging Technologies
11:45 – 12:10 Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification

Authors: Vineesh V S, Binod Kumar, Rushikesh Shinde, Akshay Kumar Jaiswal, Harsh Bhargava and Virendra Singh

 

Hierarchical State Space Checks for Errors in Sensors, Actuators and Control of Nonlinear Systems: Diagnosis and Compensation

Authors: Md Momtaz and Abhijit Chatterjee

Iterative Parallel Test to Detect and Diagnose of Multiple Defects for Digital Microfluidic Biochip

Authors: Sourav Ghosh, Dolan Maity, Arijit Chowdhury, Surajit Kumar Roy and Chandan Giri

12:10 – 12:35 Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification

Authors: Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui and Christian Sauer

A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits

Authors: Sayandeep Sanyal, Amit Patra, Pallab Dasgupta and Mayukh Bhattacharya

Detailed Fault Model for Physical Quantum Circuits

Authors: Arighna Deb and Debesh Kumar Das

12:35 – 12:45 END