|Title: Enabling Efficient, High-Quality Test of Chiplet-based Server SoCs
As the pace of integration on a monolithic die as governed by Moore’s Law slows down due to complexity, increased cost and reduced benefits, new techniques such as chiplet based designs have emerged. Chiplets enable partitioning of a design into disparate pieces and permit manufacturing of these partitions in heterogenous technology nodes that are best suited for them based on their functionality. For example with chiplet technique a die containing memory controller/High-Speed IOs/data fabric can be on an older technology node compared to the die containing CPU core and cache. Chiplets also unlock flexibility of packaging an IO die with varying number of CPU core dice to service markets at different performance and price points. Testing of chiplet based packages pose some unique challenges that need to be comprehended early on and solutions for which need to be integrated into the chiplets as well as packaging. This talk will give a brief overview of the chiplet based AMD EPYC server & high-end desktop SoC and go over some of the solutions that have been incorporated to enable efficient & high-quality test.
Nagesh Tamarapalli has been with AMD India Design Center since 2006. He is currently a Senior Fellow and leads DFT and manufacturing test for AMD server SoCs. Prior to AMD, he was with Mentor Graphics DFT group for about a decade where he worked on logic BIST, test kompression and diagnosis tools. A paper he co-authored at International Test Conference 1999 on logic BIST was awarded Honorable Mention Award. He is also a co-inventor of 18 approved US patents in the area of testing. He holds MS in Electrical Engineering from Indian Institute of Technology, Kharagpur, India and PhD in Electrical Engineering from McGill University, Montreal, Canada.