|Title: Post Silicon Considerations for Low Power SoCs
The post silicon test of low power SoCs is challenging for various reasons. Some of the challenges include the need for test at the multiple power states defined for the product, testing within the functional power budget of the design and maintaining a tight control over the test cost, product quality and yield. This presentation will give an overview of these challenges and how DFT & post silicon methodologies can help to address them.
Jais Abraham is Director of Design Engineering at Qualcomm India Pvt. Ltd., where he focuses on the Design-For-Test methodology. After graduating in Electronics Engineering from IIT- Chennai, he worked at Texas Instruments, AMD and most recently at Intel, looking into the DFT of various classes of products ranging from extremely cost-sensitive products to high speed processors and also products with stringent quality requirements. Jais has co-authored multiple technical papers in various conferences and is an co-inventor of 6 patents.