|Title: Challenges of Test Cost/DPM and Artificial Intelligence
With increased complexity of current SoC designs, process technology several new defect mechanism result in extremely high test cost to be able to screen defects.
Anand Bhat, Senior Director of Engineering, Intel India, leads the Product Engineering division at Intel’s Bangalore design center. In his current role, he is responsible for delivering various products in enablement of post Si aspects to release to volume, executing best in class test cost and DPM through wafer level and package level test. In the past years, he was leading Design for Test for IOT division. Prior to joining Intel, he has served as Director of Engineering at Qualcomm, Senior Manager, DFT at Texas Instruments. Anand has overall 18+ years of experience in VLSI industry specializing in Design for Test (DFT). He has been part of driving many innovations, 10 inventions, with more than 5 granted patents. He has authored several papers in various technical conferences. He holds Bachelor degree from SDM College, Dharwad.